The plateau variant is specifiable, but as written its exit rule cannot fire — and it has n=1 testable cycle
The question
Verbatim: "Test the 'HBM has broken the cycle' plateau hypothesis as an explicit backtest variant (current cycle does not crash; exit only on China-entrant disconfirmation or smart-money exit)."
Context: this is open follow-up #5 of [[2026-06-28-chip-memory-cycle-phase2-phase3-indicators]], itself inheriting a follow-up from the memory-cycle v1.1 phase-history notes. The lead RDCO investing thesis is the chip-fab/memory capital cycle at position/capital-cycle horizon, currently judged Phase 2.
What we already know (from the vault)
- The variant already exists in two non-identical wordings, and the vault has never reconciled them. The original ([[phase-history-notes]]) reads "current cycle does not crash, force exit only on smart-money disconfirmation." The parent brief added the China-entrant leg. A third, narrower version in [[2026-07-07-dram-hbm-phase2-phase3-early-signals]] asks only that the pipeline "encode the Phase-2-plateau state" so it stops manufacturing a crash date. These are three different asks: a strategy variant, an exit-rule swap, and a state-machine fix.
- The base strategy has already been tested and told not to deploy. [[2026-05-18-memory-cycle-v1.1-v2-honest-rerun]] (mode A, 6 cycles, 112 simulated trades) put mean strategy return at +246.8% (95% bootstrap CI +15.9% to +649.5%) against buy-and-hold of the same universe at +273.9% (CI +50.3% to +632.1%). The rules beat buy-and-hold in 2 of 6 cycles. Leave-one-out: dropping the 2024-current cycle takes the strategy mean to +51.6%, a -195.2pp collapse. The verdict was "DO NOT DEPLOY v1.1 AS A MECHANICAL STRATEGY," with a recommended Path A of buy-and-hold plus an anchor-break kill switch.
- v1.1 already has no price-based exit. [[2026-05-18-memory-cycle-v1.1]] exits only on anchor breaks: four HIGH-severity conditions (close the bucket) and four MEDIUM (trim to 1R), where any one fires a founder review and any two confirmed across 1-2 quarters closes the position. The plateau variant is therefore not a new exit philosophy; it is a narrowing of an already-discretionary one.
- The China-entrant leg was re-derived and largely invalidated three weeks ago. [[2026-09-08-cxmt-ymtc-bit-share-phase3-threshold]] replaces the asserted 12-15% CXMT bit-share trigger with a joint condition (roughly 15-22% share and industry bit-demand growth already decelerated to 18% or below), then states the inversion outright: on that arithmetic there is no reachable CXMT DRAM bit share that triggers Phase 3 against strong demand. China is a threshold-lowering variable worth roughly 3-6 percentage points of demand-deceleration tolerance, not a trigger. Separately, the entrant trigger has already fired on NAND: YMTC reached 14% of global NAND bit shipments (Counterpoint Q2 2026, published 2026-08-12).
- As of September 2026, zero Phase-3 triggers have fired, with two flickers. Micron total days-inventory-outstanding sits at its own trailing-8-quarter minimum with work-in-process days +5.4% off floor against a +10% threshold ([[2026-09-07-memory-supplier-inventory-days-dio-anchor]]); capex shell-share ran 38.4-51.8% ex-acquisition against a 45% threshold, the first genuine flicker on that indicator ([[2026-09-06-vendor-capex-composition-memory-anchor]]); contract-price deceleration is 1 of 2 required quarters.
What the web says
- Trade press reports that Samsung, SK Hynix and Micron have sold out DRAM and high-bandwidth-memory (HBM) capacity for all of 2027, with long-term agreements (LTAs) running as long as five years (TweakTown, Macrostream). This is the plateau case's load-bearing external claim and it is secondary-sourced throughout.
- TrendForce has conventional DRAM contract pricing decelerating but still rising: +58-63% QoQ in 2Q26 to a forecast +13-18% in 3Q26, with 2027 HBM4 contract prices expected to rise sharply, potentially doubling (TrendForce).
- The most detailed cycle-position tracker (LuminixAI, July 2026, flagged promotional) puts the cycle at ~36 months from the mid-2023 trough versus a 30-month record for the 2018 supercycle, and reports none of its three tier-1 exit triggers fired. Supplier inventories 3-5 weeks against a 10-15+ week pre-downturn norm; customer-side inventories 7-9 weeks, just under an 8-10 week warning band. Its probability-weighted peak moved from H1 2027 to ~Q3 2027 (Luminix).
- The clearest structural-break case names five mechanisms: non-bounded artificial-intelligence inference demand, exponential per-accelerator memory scaling, HBM's wafer-area penalty plus chip-on-wafer-on-substrate packaging as a supply governor, multi-year contracts, and demand elasticity (UncoverAlpha, March 2026). Critically, that same author still expects a correction: 15-25% revenue decline with margins compressing to 35-40%, versus historical 30-40% declines and sub-25% margins. Historical equity drawdowns cited: 60-80% (1996), ~56% (2018), ~50% (2022).
- Dr. Robert Castellano's original "HBM Has Broken the Memory Cycle: Why This Shortage Is Different" is a Substack piece, not affiliated with an institutional research house. The vault has never ingested it. The hypothesis has been carried secondhand through four months of RDCO documents on the strength of a title.
Convergences and contradictions
- Converge: vault anchors and every independent tracker agree that as of September 2026 no Phase-3 trigger has fired. On the question "are we still in Phase 2," there is no dispute worth trading against.
- Contradict — the LTA leg is unresolved inside the vault. [[2026-05-18-hbm3e-hbm4-capacity-timeline-phase-b-end]] states that the fact which would force capitulation to the bull case, a hyperscaler signing a 3+ year fixed-price HBM offtake, has not happened. The honest-rerun doc nonetheless cites "multi-year offtakes" as plateau evidence. Trade press now claims five-year LTAs. Three sources, three positions, no reconciliation. The plateau case leans hardest on the leg with the weakest evidentiary chain.
- Contradict — "plateau" and "no drawdown" are not the same claim, and the variant conflates them. Even the structural-break bull expects a 15-25% revenue decline. Prior-cycle equity drawdowns ran 50-80%. A variant whose exit rule is designed never to fire will sit through the entire correction the hypothesis itself predicts.
Synthesis for RDCO
The variant is specifiable, and here is the spec. Universe: point-in-time US-listed memory names per the v1.1 construction rule (MU, SMH, SNDK, INTC as the live basket; WDC, STX, MRVL in the backtest universe). Entry: unchanged from v1.1 tranches (0.5R initial, scale-in at -5%, full at -10%, 1R = $5,000, 4R bucket cap). Exit, as literally worded in the question: (a) China-entrant disconfirmation, or (b) smart-money exit. Sizing, benchmarks and reporting inherit the [[investing-backtest-thesis]] v2 contract — dual benchmarks (buy-and-hold universe and SMH/SPY), mandatory leave-one-out, trade-count-aware precision, no 2-decimal Sharpe below 50 trades. Mode A, fixed-rule, no parameter fitting.
But as literally worded, neither exit leg can function. Leg (a) is arithmetically unreachable on DRAM: the September 8 derivation says no CXMT bit share triggers Phase 3 against strong demand, so scoped to DRAM the leg never fires. Scoped to NAND it has already fired, because YMTC crossed 14% in August. A rule that is either never-true or already-true depending on an unstated scope is not a rule; it is a placeholder. Leg (b) is weaker still: in v1.1, "2+ tracked smart-money managers exit the same name in the same quarter" is a MEDIUM-severity signal that trims to 1R and awaits a second signal, and 13F filings arrive roughly 45 days after quarter end. Against an asset class that has repeatedly fallen 50-80% inside 12-18 months, a lagged trim-to-1R is not an exit. So the honest characterisation of the variant as specified is: an unconditional hold with decorative exits. That may still be the right posture. It should be named as such rather than dressed as a rule set.
The statistical ceiling is the finding, and it is hard. This variant cannot be backtested in any meaningful sense. Its claim is about one cycle, the live one, and n=1. Every prior cycle in phase-history.csv terminated in a dateable down-cycle by construction, so running the plateau variant over 1997, 2001, 2008, 2018 and 2022 does not test the hypothesis; it measures the cost of being wrong about it. That counterfactual is worth computing and is already latent in the honest rerun: the buy-and-hold-universe column is the never-exit case, and it returned +86.7% / +38.0% / +90.4% / +286.6% / +14.5% / +1127.1% across the six windows, beating the v1.1 rules in 4 of 6. That is real evidence for the posture (holding beat trading) and none at all for the hypothesis (that this cycle does not crash). Two caveats keep it from being stronger than that: the windows are phase-aligned and end after recovery, which flatters a holder who never had to mark to market at the trough, and the honest rerun does not report per-cycle maximum drawdown for the buy-and-hold benchmark, so the survivability of the hold is unmeasured. Per [[2026-06-01-cpcv-deflated-sharpe-autoinv-validation]], the correct output for a book at this horizon is "here are the cycles, one by one, and here is the leave-one-out" — not a deflated Sharpe. Wiring any Sharpe-family statistic to a one-cycle hypothesis would be exactly the false rigor the v2 harness was built to forbid.
What this changes. The marginal question is smaller than the follow-up implied. Path A of the honest rerun (buy-and-hold plus HIGH-severity anchor kill switch) is already most of the plateau variant. The delta between Path A and the plateau variant is only whether the two named legs replace the four HIGH-severity anchor triggers, and with n=1 that comparison cannot be resolved empirically. The defensible move is to convert the variant from a backtest into a pre-registered forward test: write the exit rule down now, with the scope ambiguity resolved and a price-based backstop added, timestamp it before the end-September 2026 quarterly review, and let the live cycle produce the seventh data point. That does not require and does not imply any paper-trade deployment; it is a documentation act. Three spec defects must be inherited deliberately if a run happens anyway: the days-inventory-outstanding unit is incompatible with the "5-6 weeks" tripwire row and will read as permanently triggered if dropped in; the China row must split into 5a (DRAM/CXMT, joint condition) and 5b (NAND/YMTC, already crossed); and the LTA leg must be marked unresolved rather than asserted.
Why this is in the vault
It closes open follow-up #5 of [[2026-06-28-chip-memory-cycle-phase2-phase3-indicators]] and the matching follow-up in the memory-cycle v1.1 phase-history notes, and it determines what the end-September 2026 quarterly anchor review is allowed to conclude: specifically, that the choice between holding through and exiting on schedule cannot be settled by any run of the [[investing-backtest-thesis]] harness, so it stays a founder judgment call rather than becoming a harness output.
Open follow-ups
- Ingest Castellano's primary piece. The hypothesis has driven four vault documents on the strength of its title. Read "HBM Has Broken the Memory Cycle: Why This Shortage Is Different," extract the actual mechanisms and any thresholds the author names, and check whether he has revised it since.
- Resolve the LTA contradiction. Does a 3+ year fixed-price hyperscaler HBM offtake exist as of September 2026? Primary source (10-Q/10-K commitment disclosures, earnings-call transcripts), not trade press. This is the single fact that most moves the plateau prior.
- Compute per-cycle maximum drawdown for the buy-and-hold-universe benchmark in the honest rerun. Without it, "holding beat trading in 4 of 6 cycles" is a return statement with no survivability statement attached.
- Write the pre-registered forward-test rule with the China leg scope-resolved (DRAM vs NAND), a price-based backstop, and a hard timestamp, so the live cycle yields a clean seventh observation instead of a retrospectively-rationalised one.
- Decide whether the plateau variant should replace or supplement the four HIGH-severity anchor triggers. Framed as a decision with named consequences, since it cannot be framed as a test.
- Refresh the pricing anchor. The freshest DRAM/HBM pricing in any vault memory document is July 2026, leaving a two-month blind spot as of today.
Related
- [[2026-06-28-chip-memory-cycle-phase2-phase3-indicators]]
- [[2026-05-18-memory-cycle-v1.1]]
- [[2026-05-18-memory-cycle-v1.1-v2-honest-rerun]]
- [[phase-history-notes]]
- [[2026-09-08-cxmt-ymtc-bit-share-phase3-threshold]]
- [[2026-09-07-memory-supplier-inventory-days-dio-anchor]]
- [[2026-09-06-vendor-capex-composition-memory-anchor]]
- [[2026-07-07-dram-hbm-phase2-phase3-early-signals]]
- [[2026-05-18-hbm3e-hbm4-capacity-timeline-phase-b-end]]
- [[2026-07-15-capex-financing-layer-as-memory-cycle-phase-marker]]
- [[2026-06-01-cpcv-deflated-sharpe-autoinv-validation]]
- [[investing-backtest-thesis]]
Sources
Vault
~/rdco-vault/06-reference/research/2026-06-28-chip-memory-cycle-phase2-phase3-indicators.md— parent brief; open follow-up #5 is this question verbatim~/rdco-vault/01-projects/investing/anchors/memory-cycle-v1.1/phase-history-notes.md— original variant wording; regime-change-risk section; phase definitions~/rdco-vault/01-projects/investing/anchors/memory-cycle-v1.1/phase-history.csv— 36 labelled transitions across 6 cycles; no down-cycle row for 2024-current~/rdco-vault/01-projects/investing/theses/2026-05-18-memory-cycle-v1.1.md— entry tranches, HIGH/MEDIUM exit anchors, sizing, phase labels~/rdco-vault/01-projects/investing/backtests/2026-05-18-memory-cycle-v1.1-v2-honest-rerun.md— 6-cycle mode-A results, bootstrap CIs, leave-one-out, survivorship confession, Path A/B recommendation~/rdco-vault/06-reference/research/2026-09-08-cxmt-ymtc-bit-share-phase3-threshold.md— 15-22% joint condition; "no reachable share triggers Phase 3 against strong demand"; YMTC 14% NAND~/rdco-vault/06-reference/research/2026-09-07-memory-supplier-inventory-days-dio-anchor.md— Micron DIO 120.5d, WIP +5.4% off floor, unit-incompatibility defect~/rdco-vault/06-reference/research/2026-09-06-vendor-capex-composition-memory-anchor.md— shell_share 38.4-51.8% ex-acquisition vs 45% threshold~/rdco-vault/06-reference/research/2026-07-07-dram-hbm-phase2-phase3-early-signals.md— 5-row tripwire scoreboard; announce-vs-online re-key~/rdco-vault/06-reference/research/2026-05-18-hbm3e-hbm4-capacity-timeline-phase-b-end.md— Phase-B end window Q3 2026-Q2 2027; "no 3+ year fixed-price offtake has happened"~/rdco-vault/06-reference/research/2026-07-15-capex-financing-layer-as-memory-cycle-phase-marker.md— financing kill-switch the physical anchors cannot see~/rdco-vault/06-reference/research/2026-06-01-cpcv-deflated-sharpe-autoinv-validation.md— what to report instead of a deflated Sharpe on a few-trade capital-cycle book~/.claude/skills/investing-backtest-thesis/SKILL.md— v2 harness contract: per-window universe, phase-aligned windows, mandatory leave-one-out, trade-count-aware precision
Web
- https://drrobertcastellano.substack.com/p/hbm-has-broken-the-memory-cycle-why — the hypothesis's primary source (located, not yet read)
- https://www.uncoveralpha.com/p/every-memory-cycle-ends-the-same — five structural-break mechanisms; historical drawdown base rates
- https://www.useluminix.com/reports/industry-analysis/dram-cycle-position-analysis-peak-timing-indicators — cycle-position tracker, July 2026 (promotional framing flagged)
- https://www.trendforce.com/presscenter/news/20260602-13074.html — HBM contract-price trajectory into 2027
- https://www.tweaktown.com/news/113004/memory-capacity-for-all-of-2027-has-reportedly-been-booked-and-sold-with-no-more-dram-or-hbm-available/index.html — 2027 sold-out claim
- https://www.macrostream.ai/articles/6a71367feca65502ee48c260 — LTA duration claim (up to 5 years)