The Chinese-supply Phase-3 threshold: CXMT can't reach it on DRAM, and YMTC already crossed it on NAND

The question

"Quantify the CXMT/YMTC volume trajectory and the bit-share threshold at which Chinese memory supply becomes the exogenous Phase-3 trigger the oligopoly can't discipline."

Context: [[2026-07-03-cxmt-dram-capacity-memory-oligopoly-risk]] established the level (CXMT ~9-11% DRAM bit share, >30% cost-per-bit gap, HBM two generations behind) and closed by naming the missing number: the bit share at which Chinese supply flips the market from undersupply to balance. This brief derives that threshold arithmetically instead of asserting it, and it separates the DRAM question (CXMT) from the NAND question (YMTC), which turn out to have opposite answers.

What we already know (from the vault)

• The parent brief's finding, not to be re-reported: CXMT reads as a Phase-3 accelerant, not a Phase-2 breaker. HBM is structurally protected (no EUV, no leading-edge base die, HBM3 mass production slipped past 2026); the exposure is on the commodity-DDR flank, and it "activates on a state-change, not a level" [[2026-07-03-cxmt-dram-capacity-memory-oligopoly-risk]].
• The vault's current threshold is an assertion, not a derivation. Tripwire row 5 reads: "CXMT DDR5 cost-per-bit within ~10% of big three AND bit-share >~12-15%, OR a big-three contract crack not confined to the secondary/module channel" [[2026-07-07-dram-hbm-phase2-phase3-early-signals]]. No supply/demand arithmetic sits behind the 12-15%. Replacing that with a derived, demand-conditional band is this brief's job.
• The thesis's China disqualifier is HBM-keyed and therefore nearly unfireable. v1.1's exit table lists "CXMT or YMTC achieves volume HBM3E-equivalent production" at Medium severity, founder-review, trim to 1R [[2026-05-18-memory-cycle-v1.1]]. The parent brief already recommended re-keying it. The arithmetic below says the commodity bit-share condition, not the HBM condition, is the one that can actually fire in the thesis window.
• The two freshest supply-side anchors do not move the threshold. Micron's DIO reads zero triggers, with finished-goods days at 8.7 (the lowest in the fifteen-year record) and only a WIP-days flicker at roughly a third of calibrated magnitude [[2026-09-07-memory-supplier-inventory-days-dio-anchor]]. Vendor capex composition produced its first genuine flicker (shell share 38.4-51.8% ex-acquisition against a 45% threshold) but equipment-not-placed-into-service is up only 3.7% YoY, so tools are not queued [[2026-09-06-vendor-capex-composition-memory-anchor]]. Both are big-three-internal signals. Neither observes the exogenous entrant at all, which is precisely the instrumentation gap this brief addresses.
• Standing doctrine on the denominator: 2026 DRAM capex (~$61.3B, +14% YoY) has "minimal impact on bit supply growth" because it buys node migration and TSV/HBM packaging rather than greenfield wafers [[2026-06-28-chip-memory-cycle-phase2-phase3-indicators]]. Big-three bit-supply growth is being deliberately suppressed, which is the reason a 10%-share entrant matters at all.

What the web says

Trajectory refresh (the vault's numbers were as of July 2026):

• CXMT (DRAM). ~265k wafer starts/month (wspm) at end-2025, on track for ~350k wspm by end-2026 (about 25k below Micron), and ~420k wspm in 2027, which is roughly 17% of global DRAM wafer capacity against ~13% in 2025. Bit-shipment share tracks well below that: ~9% (2025) rising to ~12% (2027), per SemiAnalysis via secondary coverage (Yahoo Finance / Tom's Hardware summarising SemiAnalysis; SemiAnalysis).
• CXMT is now doing its own HBM crowd-out. CXMT HBM capacity is put at ~30k wspm by end-2026 and ~55k wspm by end-2027, i.e. ~9% then ~13% of its own wafer base, consumed at roughly 3x wafer area per gigabit. The same mechanism that suppresses big-three commodity bit output now suppresses CXMT's (same secondary coverage of SemiAnalysis, above).
• Revenue share lags bit share lags capacity share. Counterpoint put CXMT at 8% of DRAM revenue in Q1 2026, up from 3-4% in 2025, on >700% YoY revenue growth (Luminix industry analysis, Jul 5 2026). A Sept 3 2026 trade headline claims CXMT "hits 10% DRAM market share, oligopoly falls below 90% two years early" — the source returned HTTP 403 and was not read; treat the 10% as unverified and note that the headline does not specify bit vs revenue vs capacity share (TechTimes, 403 — flagged, not retried).
• YMTC (NAND) is a materially different story and the vault has never quantified it. Counterpoint's Q2 2026 tally (published Aug 12 2026) puts YMTC at 14% of global NAND bit shipments, third globally, tied with Kioxia and ahead of Micron (13%) and SanDisk (11%); Samsung 25%, SK hynix group 22%. YMTC is 5th on revenue (~13% in Q1 2026) because its mix is low-priced. Capacity: ~200k wspm across two Wuhan fabs today, ~300k wspm by early 2027, with a design target of 400-500k wspm across three new fabs (XenoSpectrum summarising Counterpoint; Yahoo Finance / Tom's Hardware).
• The forecast markets diverge in 2027, and this is the single most load-bearing external datapoint in the brief. TrendForce (Jul 30 2026) puts the DRAM sufficiency ratio at roughly -1% to -2% in 2026 with the gap widening in 2027 (tighter), while the NAND sufficiency ratio turns positive in 2027, moving NAND "from a supply-constrained environment to a more balanced market" (TrendForce, Jul 30 2026).
• The denominators for the arithmetic. DRAM bit supply growth is put at 16% for 2026 (IDC, unrevised through mid-2026); HBM wafer input rises from ~19% (2025) to ~23% (2026) of total DRAM wafers, at ~3x wafer area per gigabit versus DDR5 and ~4x for HBM4. The same report names "industry bit supply exceeding 25% YoY" as a peak condition and states supplier inventory at 3-5 weeks against a 10-15 week norm, with customer inventory at 7-9 weeks against an 8-10 week warning band (Luminix, Jul 5 2026).

Convergences and contradictions

• Convergence on DRAM: every source read agrees the DRAM gap widens through 2027 and that CXMT's capacity share runs far ahead of its bit share. Nothing found contradicts the parent brief's Phase-2-holds conclusion on the DRAM side.
• Contradiction that must be resolved before any arithmetic is done — the demand denominator. TrendForce's -1% to -2% 2026 sufficiency ratio against IDC's 16% supply growth implies constrained bit-demand growth of roughly 17-18%. The same Luminix report separately cites demand "mid-30s%", and UBS is quoted elsewhere at ~40% deliverable-constrained demand against 15-20% supply. These are not the same measure: the high numbers are unconstrained demand (what buyers would take at current prices), the low number is cleared demand. This brief uses the constrained reading (~17-18%) throughout, because the sufficiency ratio is the only figure expressed as a supply/demand identity. If the mid-30s number is the right one, every threshold below is unreachable and the question is moot — that sensitivity is stated in the synthesis rather than buried.
• The real contradiction, and the finding: the vault's tripwire row 5 sets one Chinese-entrant threshold for the whole memory complex. The data says the two markets have already separated. CXMT is at ~10-12% DRAM bit share in a market forecast to tighten; YMTC is at 14% NAND bit share in a market forecast to flip positive in 2027. The entrant threshold has not been crossed on DRAM and, on the numbers below, cannot be crossed on DRAM inside the thesis window. On NAND it has already been crossed and the flip is inside the window.

Synthesis for RDCO

The threshold, derived rather than asserted. The market flips when industry bit-supply growth meets bit-demand growth. Decompose supply growth as a share-weighted sum: g_supply = w·g_china + (1−w)·g_bigthree, where w is the Chinese entrant's bit share. Set g_supply ≥ g_demand and solve for w. Inputs, all named and all estimates: g_demand = 18% (backed out of TrendForce's -1 to -2% sufficiency against IDC's 16% supply, not independently sourced); g_bigthree = 12% (the residual after removing CXMT's contribution from the 16% total, and consistent with the vault's "capex buys nodes and TSV, not wafers" doctrine); g_cxmt = 40% (wafer adds of +32% in 2026 decelerating to +20% in 2027, times a ~10-15%/yr density gain capped below the big three's historical ~20% by the absence of EUV, minus 3-5pp for CXMT's own HBM crowd-out at 9-13% of its wafer base). The wspm-to-bits conversion is bit growth ≈ wafer growth × (1 + density gain) − HBM allocation drag; this is the weakest link in the chain and the honest error bar on g_cxmt is roughly ±10pp.

Solving: 0.12 + 0.28w ≥ 0.18 gives w ≥ ~21%. Running the corners — g_demand 16-20%, g_cxmt 35-50%, g_bigthree 12-14% — produces a band of CXMT DRAM bit share of roughly 15% to 22%, and only when industry bit-demand growth has already decelerated to 18% or below. State it as a joint condition, because that is what it is: CXMT bit share above ~15-20% while DRAM bit-demand growth is at or below ~18%. CXMT is forecast at ~12% in 2027, so the share leg is a 2028-2029 event on the current wafer cadence, not a thesis-window event. This replaces the vault's asserted 12-15% band, which is too low by roughly a third and, more importantly, was stated as a level when it is a conditional.

But the sensitivity analysis is the actual finding, and it inverts the framing. Run the same equation with w = 0: with no Chinese supply at all, the market flips when demand growth falls below the big three's ~12%. With CXMT at 12% share growing 40%, supply growth is 15.4% and the flip needs demand below 15.4%. At 20% share, 17.6%. So CXMT's real effect is not that it causes the flip; it is that it buys roughly 3-6 percentage points of demand-deceleration tolerance out of the market. It converts a demand disappointment that would previously have been absorbed into one that flips the sufficiency ratio. Push it to the limit: even at 25% share growing 50%, industry supply growth reaches only ~21.5%, still short of a mid-20s demand number. On this arithmetic there is no reachable CXMT bit share that triggers Phase 3 against strong demand. China is a threshold-lowering variable, not a trigger. The trigger, on DRAM, remains a demand event. That is a meaningfully different instruction than "watch CXMT's share," and it argues for keeping the hyperscaler-capex demand anchor senior to any China anchor in the trigger stack.

The NAND side is where the question actually has a yes. YMTC sits at 14% of global NAND bit shipments as of Q2 2026, third worldwide, with wafer capacity going 200k to ~300k wspm by early 2027 — a +50% wafer add, before layer-count gains. At 14% share and plausible bit growth of 50-70%, YMTC alone contributes 7-10 percentage points of NAND industry bit-supply growth, against a typical industry rate in the mid-to-high teens. That is roughly half of all NAND supply growth coming from one sanctioned entrant with a deliberately low-priced mix (13% revenue share on 14% bit share is the price-taker signature). TrendForce's forecast that the NAND sufficiency ratio turns positive in 2027 is the same finding arriving from the other direction. The exogenous-entrant Phase-3 trigger the June 28 brief was looking for has already fired — on NAND, via YMTC, and the vault never quantified YMTC because the thesis is DRAM/HBM-anchored. The cascade the thesis relies on runs HBM to DDR5 to DDR4 to NAND; its tail is being cut off by a supplier the oligopoly cannot discipline, roughly two years before the DRAM core is exposed.

Position implications, on a multi-quarter clock. Nothing here trips a v1.1 disqualifier and posture is unchanged; every big-three-internal anchor still reads deep Phase 2. Three changes to the instrumentation, all reversible and all cheap. First, split tripwire row 5 into 5a (DRAM/CXMT) and 5b (NAND/YMTC) and re-key 5a to the derived joint condition above; a single blended China row is now provably wrong. Second, the basket carries name-specific NAND exposure the DRAM thesis does not cover: v1.1's ticker set is MU + SMH + SNDK + INTC, and SanDisk is a NAND pure-play at 11% bit share sitting directly in front of a market TrendForce says balances in 2027, while Micron's NAND book is a minority of a mostly-DRAM company. If the NAND read is right, SNDK and MU stop being correlated expressions of one cycle in 2027. That is a founder-judgment item, not a Ray execution item, and it is the only thing in this brief worth his attention this quarter. Third, track CXMT's bit-share-to-capacity-share ratio, not its bit share. SemiAnalysis's own path implies roughly 0.7 in both 2025 (9/13) and 2027 (12/17), i.e. CXMT is forecast to close approximately none of its density gap. Rounded whole-percent inputs make the exact ratio meaningless, but the flatness is the forecast, and a ratio climbing toward 0.85 would mean CXMT's bit output accelerating with no new wafers at all. That is an earlier and cleaner tripwire than the share level, because it fires on the mechanism rather than the outcome.

Falsifiability — what would tell the founder the threshold has been crossed, and when it would appear.

Indicator 3 is the highest-value and cheapest of the five because it tests the NAND decoupling directly, publishes monthly rather than quarterly, and requires no subscription-gated share data. Indicator 2 is the one that tests the DRAM threshold, and on the trajectory above it should not fire before 2028. If it fires in 2027, the derivation here is wrong and the density-gain assumption is the first place to look.

Why this is in the vault

It re-keys tripwire row 5 of [[2026-07-07-dram-hbm-phase2-phase3-early-signals]] from an asserted 12-15% bit-share level to a derived joint condition, splits it into separate DRAM and NAND rows, and surfaces a specific founder-judgment item on the memory-cycle-v1.1 ticker basket: SNDK is a NAND pure-play in front of a market TrendForce forecasts will balance in 2027 for reasons the DRAM-anchored thesis does not model.

Open follow-ups

• The demand denominator is the whole ballgame and it is sourced from one inference. Establish whether constrained DRAM bit-demand growth of ~17-18% can be corroborated from a second independent source, or whether it exists only as a back-out from TrendForce's sufficiency ratio. Every number in this brief moves with it.
• Build the YMTC/NAND supply anchor the vault does not have. Counterpoint's quarterly bit-shipment table is the series; determine whether it is reachable without a subscription, and whether YMTC's IPO prospectus (in progress per Sept 2026 trade press) discloses wafer starts and bit output directly, which would upgrade this from Tier C commentary to a primary source.
• Does SNDK belong in a DRAM/HBM thesis at all after 2027? Full name-level review of the v1.1 basket against the NAND/DRAM divergence, not just a trim decision.
• Verify CXMT's HBM wafer allocation independently. The 30k/55k wspm figures come from secondary coverage of one house and materially suppress CXMT's commodity bit growth in the derivation. If wrong in either direction, the threshold band moves by several points.
• Confirm or kill the "CXMT at 10% DRAM share" September claim blocked by a 403 here, and pin down whether it is bit, revenue, or capacity share. Sources conflate the three constantly and the vault should record only bit share.
• Re-key the v1.1 China disqualifier from "volume HBM3E-equivalent production" (nearly unfireable, per the parent brief) to the derived commodity bit-share joint condition, and add a separate NAND row keyed to YMTC.
• Does the density-gap-closure rate have a published proxy? The bit-share-to-capacity-share ratio proposed above needs both numerator and denominator from the same house in the same period or it is noise.

Related

• [[2026-07-03-cxmt-dram-capacity-memory-oligopoly-risk]] — the direct parent; established the level this brief converts into a threshold
• [[2026-06-28-chip-memory-cycle-phase2-phase3-indicators]] — the brief that surfaced this question and named Chinese entrants as the exogenous Phase-3 agent
• [[2026-07-07-dram-hbm-phase2-phase3-early-signals]] — the tripwire table whose row 5 this brief re-keys and splits
• [[2026-05-18-memory-cycle-v1.1]] — the executable thesis, its ticker basket, and the HBM3E-keyed China disqualifier
• [[2026-09-07-memory-supplier-inventory-days-dio-anchor]] — freshest supply-side anchor; zero triggers, checked against this threshold
• [[2026-09-06-vendor-capex-composition-memory-anchor]] — capex-composition anchor; first flicker, tools not queued
• [[2026-06-23-stratechery-memory-chips-china-microsoft-deepseek]] — origin of the YMTC "2x NAND capacity by end-2027" datapoint this brief quantifies

Sources

Vault

• [[2026-07-03-cxmt-dram-capacity-memory-oligopoly-risk]] — ~/rdco-vault/06-reference/research/2026-07-03-cxmt-dram-capacity-memory-oligopoly-risk.md
• [[2026-06-28-chip-memory-cycle-phase2-phase3-indicators]] — ~/rdco-vault/06-reference/research/2026-06-28-chip-memory-cycle-phase2-phase3-indicators.md
• [[2026-07-07-dram-hbm-phase2-phase3-early-signals]] — ~/rdco-vault/06-reference/research/2026-07-07-dram-hbm-phase2-phase3-early-signals.md
• [[2026-05-18-memory-cycle-v1.1]] — ~/rdco-vault/01-projects/investing/theses/2026-05-18-memory-cycle-v1.1.md
• [[2026-09-07-memory-supplier-inventory-days-dio-anchor]] — ~/rdco-vault/06-reference/research/2026-09-07-memory-supplier-inventory-days-dio-anchor.md
• [[2026-09-06-vendor-capex-composition-memory-anchor]] — ~/rdco-vault/06-reference/research/2026-09-06-vendor-capex-composition-memory-anchor.md
• [[2026-06-23-stratechery-memory-chips-china-microsoft-deepseek]] — ~/rdco-vault/06-reference/2026-06-23-stratechery-memory-chips-china-microsoft-deepseek.md

Web

• Diverging Memory Market Outlook in 2027 as DRAM Supply Remains Tight While NAND Flash Supply Conditions Ease — TrendForce, Jul 30 2026
• DRAM Cycle Mid-2026 Update: Pricing, Inventory & Peak Timing — Luminix, Jul 5 2026
• China's YMTC Ranks 3rd Globally in NAND Bit Shipments — 14% Share — XenoSpectrum, summarising Counterpoint Aug 12 2026
• CXMT close to matching Micron's memory capacity in 2026 — Yahoo Finance / Tom's Hardware, summarising SemiAnalysis
• China's YMTC moves to break free of U.S. sanctions, aims for 15% of NAND by late 2026 — Yahoo Finance / Tom's Hardware
• China's CXMT Is Set to Challenge DRAM Incumbents — SemiAnalysis
• CXMT Hits 10% DRAM Market Share — TechTimes, Sept 3 2026 — HTTP 403, not read, claim unverified