The Phase 2 → Phase 3 tripwire set for the DRAM/HBM capital cycle — one flicker, zero triggers as of July 2026

The question

What are the 3-5 most concrete, monitorable early-signal metrics that would mark the DRAM/HBM capital cycle's transition from Phase 2 (capacity being announced/built, ASP still rising) to Phase 3 (capacity-online / glut / ASP rollover — the cycle top and down-leg)? And as of mid-2026, have any triggered? The goal is to formalize the Phase 3 trigger set before it arrives, so the Markov Layer-1 phase-tracker fires on a defined observable rather than on narrative after the fact.

Framing note: this uses the Markov pipeline's P1→P4 ladder (P1 tight-supply/rising-ASP → P2 capacity-announcements [←here] → P3 capacity-online/glut/ASP-rollover → P4 capex-cuts/rationalization) from [[2026-05-27-markov-equities-pipeline-spec]]. The memory-cycle-v1.1 thesis uses a differently-numbered 3-phase label (Tightness/Plateau/Rollover); its "Rollover" == this brief's Phase 3.

What we already know (from the vault)

The June 28 indicator brief already built a working trigger set and concluded every primary signal still read deep-Phase-2 (prices accelerating up, >40wk lead times, allocation-only, inventories at 2018 supercycle lows, meaningful new wafer capacity dated to H2 2027+). Its key structural insight: this cycle's capex is rising (+14% DRAM) but going to node migration + HBM packaging, not greenfield wafers — so the classic "capex → wafer glut" Phase-3 trigger has not engaged. Watch capex composition, not dollar level [[2026-06-28-chip-memory-cycle-phase2-phase3-indicators]].
The executable thesis encodes the Phase-3 markers directly as its exit anchors: hyperscaler combined capex revised DOWN >10% for 2+ consecutive quarters; oversupply announced by 2+ vendors; DRAM contract prices declining 4+ consecutive months; HBM capacity-online matching/exceeding demand; a maker announcing expansion that closes the bottleneck in <18 months [[2026-05-18-memory-cycle-v1-1]].
The phase-history methodology gives the historically-applied mechanical rule for down-cycle entry: "DRAM spot declining 6+ consecutive months OR vendor margin compression >30%," with capacity-announcement = "vendor publicly commits >20% capacity increase." It also flags the live regime-change risk: disciplined-oligopoly + HBM economics may hold this cycle in a Phase-2 plateau structurally longer than the 4-6 prior cycles, so the pipeline must carry an explicit plateau state and not manufacture a crash date [[2026-05-18-memory-cycle-v1-1-phase-history-notes]].
The capacity-timeline brief named the best-evidence Phase-B-end window as Q3 2026 – Q2 2027, with Samsung's +47% HBM wafer ramp (170k→250k/mo by end-2026) as the borderline "<18-month bottleneck close" disqualifier; cleanest single milestone = "Samsung's 250k target hit early" [[2026-05-18-hbm3e-hbm4-capacity-timeline-phase-b-end]].
CXMT is a commodity-DDR accelerant, not an HBM Phase-2 breaker: ~9-11% bit-share, >30% cost-per-bit disadvantage, DDR5 yield-parity expected ~late 2026, HBM two generations behind and slipped past 2026. It flips from accelerant to co-trigger only if the market moves from undersupply to balance — most plausibly 2027-2028, not the next 4-8 quarters [[2026-07-03-cxmt-dram-capacity-memory-oligopoly-risk]]. Stratechery (Jun 23) is the trigger doc that flagged CXMT/YMTC as the Phase-2 disruptor variable [[2026-06-23-stratechery-memory-chips-china-microsoft-deepseek]].

What the web says

The freshest and most decision-relevant datapoint: price gains are decelerating hard, though still positive. TrendForce (Jul 3 2026) projects 3Q26 conventional DRAM contract prices +13–18% QoQ — down from 2Q26's +58–63% QoQ — explicitly citing "weaker demand from consumer applications" and "customers... reaching their affordability limit." NAND +10–15% QoQ at "a noticeably slower pace than in previous quarters." Suppliers are adopting a "more flexible pricing strategy" and PC OEMs show reduced willingness to accept increases (TrendForce Jul 3 2026).
But the direction is still UP, not a rollover. Consumer/legacy DRAM (DDR2) still forecast +35–40% in 3Q26; server DDR5 ASP still exceeds HBM profitability; 2027 HBM long-term-agreement ASP being negotiated "sharply higher" (TrendForce Jun 22 2026).
Inventory remains at crisis-tightness. Hyperscale AI buildout has drawn DRAM inventories down to single-digit weeks (vs ~8-week normal) — no lift-off from the floor yet (TrendForce via Neumonda / longyield, 2026).
Capex is still discipline-shaped in 2026. Micron $13.5B (+23%), SK Hynix $20.5B (+17%), Samsung ~$20B — going to 1-gamma node migration + TSV/HBM packaging. Only Samsung + SK Hynix can slightly expand lines; Micron's ID1 fab is not operational before 2027; "additional capex will have minimal impact on bit supply growth in 2026" (TrendForce Nov 2025).
The one genuinely new Phase-2 event: a mega greenfield announcement with a long fuse. A Korea-government initiative has SK Hynix + Samsung committing ~$575B near-term (four new fabs at ~$520B + a $53B packaging plant), part of a ~$1.3T decade plan. Critically, new bit capacity is expected to "enter the market by the end of the decade" (2029–2030). Commentary warns this build-out could make Micron's eventual "earnings downcycle... quite severe" (Motley Fool Jul 6 2026).
CXMT confirms the vault read: DDR5 yield parity expected ~late 2026, still >30% cost-per-bit disadvantage, projected to lead global bit-output growth in 2026 off a small base (~350 kwspm capacity by year-end) (SemiAnalysis / Tom's Hardware, 2026).

Convergences and contradictions

Convergence: Vault (June 28 / July 3) and web agree — no Phase-3 trigger has fired. Prices still up, inventories at supercycle lows, greenfield bit supply dated to 2027–2030, CXMT still cost-disadvantaged. The Phase-B-end window (Q3 2026–Q2 2027) and the web's "relief 2027–2028" agree the turn is not a 2026 event.
The new signal since the June 28 brief: the second derivative has turned. Price gains went from +58–63% (2Q26) to +13–18% (3Q26) QoQ. This is the earliest thing a rollover looks like — deceleration precedes decline — but it is confounded by a high base effect and consumer-demand softness, not supply relief. It is a flicker on the earliest tripwire, not a trigger.
Contradiction to hold: two Phase-2 signals are simultaneously intensifying (the $575B greenfield announcement = the "defensive land-grab that marks the end of oligopoly discipline" pattern; the largest of the cycle) AND deferred (bit supply lands 2029–2030). A huge capacity announcement with a 3-5 year fuse raises the Phase-3 prior without moving the Phase-3 clock inside the thesis window. The disciplined-oligopoly / "HBM broke the cycle" plateau hypothesis remains live.

Synthesis for RDCO

The Phase 2→3 turn is the cycle top, and it is a sequence, not a single print. Ranked earliest-turning first, here is the concrete, monitorable trigger set with mid-2026 readings and verdicts. Each is a binary observable with an explicit threshold so two raters agree (the phase-history discipline).

#	Metric	Trigger threshold	Mid-2026 reading	Verdict
1	ASP rate-of-change (2nd-derivative decel) — earliest, noisiest	QoQ contract-price gain decelerates for 2+ consecutive quarters (leads the outright rollover)	2Q26 +58–63% → 3Q26 +13–18%; consumer demand weakening; "flexible pricing"	FLICKER (1 of 2 quarters). Watch 4Q26. Confounded by base effect — do NOT treat as Phase 3 alone
2	Supplier inventory days — cleanest non-price leading indicator	DRAM inventory rises above ~5–6 weeks for 2+ consecutive quarters (off the ~3–4wk floor)	Single-digit weeks, at 2018 supercycle lows	NOT TRIGGERED. Largest distance to travel; highest-value early warning
3	*Capex composition* → greenfield bit-supply online** — disciplined-cycle-specific	2+ vendors bring greenfield wafer capacity online (not node/packaging), OR Samsung hits ~250k HBM wafer/mo on/ahead of schedule	$575B Korea announcement (Jul 2026) but bit supply dated 2029–30; 2026 capex still node/HBM, "minimal bit-supply impact"; Samsung 250k in progress	NOT TRIGGERED (announcement ≠ online). Raises the prior, not the clock. Track the online date, not the press release
4	ASP / contract-price rollover — the confirmation print	DRAM contract/spot declining 4–6 consecutive months, OR any one maker reports HBM ASP −10% QoQ (thesis + phase-history: "6+ months OR margin compression >30%")	Still rising (+13–18% QoQ in 3Q26); HBM 2027 LTAs negotiating higher	NOT TRIGGERED. The unambiguous confirm; pair with #1/#2 to distinguish a true turn from a wobble
5	Exogenous entrant (CXMT/YMTC) crossing into oversupply — the wildcard the oligopoly can't discipline	CXMT DDR5 cost-per-bit within ~10% of big three AND bit-share >~12–15%, OR a big-three contract crack NOT confined to the secondary/module channel	~9–11% bit-share, >30% cost gap, yield parity ~late 2026; only observed weakness was niche secondary modules	NOT TRIGGERED. Flips from accelerant to co-trigger most plausibly 2027–2028

Confirming (lower-priority, laggy) features that raise the prior but do not flip the state alone: lead-time/allocation normalization (currently >40wk, allocation-only — far from the ~26wk relax threshold); fab utilization softening below ~90% with new capacity online (currently sustained 95%+ = tightness); gross-margin peak-then-compress (Micron ~80%, still climbing) and equity price (noisy 1-2Q lead).

Composite decision rule for the Markov Layer-1 (do not flip on any single feature): declare P3 when (inventory rising >2Q [#2]) AND (ASP rolling over 4–6 months [#4]) — OR — when (greenfield bit-supply online / Samsung 250k hit early [#3]) AND (ASP −10% QoQ at any maker [#4]). Everything else raises the transition prior.

What this implies for the phase call: RDCO stays in Phase 2. Zero Phase-3 triggers have fired as of July 2026; exactly one earliest-tripwire flicker (#1, price-gain deceleration) has appeared — and it reads as demand-side/base-effect moderation, not supply-side relief. The nuance to internalize: the two Phase-2 signals that are moving (mega greenfield announcement + ASP deceleration) are the shape of an approaching top without being the top. The earliest plausible turn-window remains Q3 2026 – H1 2027, gated primarily on inventory days lifting off the floor (#2) and the deceleration (#1) continuing into an actual decline (#4). Position posture: unchanged; this trips no thesis exit anchor. But 4Q26 is now the first quarter that could turn the #1 flicker into a two-quarter confirmed deceleration — the earliest date the tracker's Phase-3 prior should start climbing.

Open follow-ups

Build the supplier-inventory-days time series (Micron/SK Hynix/Samsung quarterly DIO from earnings) as a structured anchor — it is the highest-value leading indicator (#2) and the vault still doesn't track it as a series. (Carried over unbuilt from the June 28 brief.)
Instrument the ASP 2nd-derivative (#1) explicitly in the DRAM-spot anchor: track QoQ-gain deceleration, not just level/direction, with a base-effect adjustment so a high-comparison quarter isn't misread as a turn.
Track greenfield bit-supply online dates for the $575B Korea fabs + Micron ID1 + Samsung P4L/P5, separate from announcement dates — the announcement (#3) already fired; the online date is the real Phase-3 clock.
Set the CXMT DDR5 yield-parity tripwire (~late 2026) and a bit-share threshold (~12–15%) at which #5 flips from accelerant to co-trigger.
Re-key the 2018 "Samsung capacity-announcement → ASP rollover" lag to calibrate the exact lead of #3 ahead of #4 for the current window.
Encode the Phase-2-plateau state as an explicit backtest variant so the pipeline doesn't force a crash date the supply curve (bit supply 2029–30) doesn't support.

[[2026-06-28-chip-memory-cycle-phase2-phase3-indicators]] — the prior indicator brief this one updates; original trigger set + "capex composition not level" insight
[[2026-07-03-cxmt-dram-capacity-memory-oligopoly-risk]] — CXMT accelerant-not-breaker analysis feeding trigger #5
[[2026-05-27-markov-equities-pipeline-spec]] — the Layer-1 phase-tracker this trigger set feeds; source of the P1→P4 ladder
[[2026-05-18-memory-cycle-v1-1]] — executable thesis; its exit anchors ARE the Phase-3 markers
[[2026-05-18-memory-cycle-v1-1-phase-history-notes]] — mechanical phase-transition rules ("DRAM spot declining 6+ months OR margin compression >30%") + regime-change caveat
[[2026-05-18-hbm3e-hbm4-capacity-timeline-phase-b-end]] — capacity-online milestone timeline (Q3 2026–Q2 2027 window); Samsung 250k disqualifier
[[2026-06-23-stratechery-memory-chips-china-microsoft-deepseek]] — trigger doc that flagged CXMT/YMTC as the Phase-2 disruptor variable

Sources

Vault

[[2026-06-28-chip-memory-cycle-phase2-phase3-indicators]] — ~/rdco-vault/06-reference/research/2026-06-28-chip-memory-cycle-phase2-phase3-indicators.md
[[2026-07-03-cxmt-dram-capacity-memory-oligopoly-risk]] — ~/rdco-vault/06-reference/research/2026-07-03-cxmt-dram-capacity-memory-oligopoly-risk.md
[[2026-05-27-markov-equities-pipeline-spec]] — ~/rdco-vault/01-projects/investing/2026-05-27-markov-equities-pipeline-spec.md
[[2026-05-18-memory-cycle-v1-1]] — ~/rdco-vault/01-projects/investing/theses/2026-05-18-memory-cycle-v1-1.md
[[2026-05-18-memory-cycle-v1-1-phase-history-notes]] — ~/rdco-vault/01-projects/investing/anchors/memory-cycle-v1-1/phase-history-notes.md
[[2026-05-18-hbm3e-hbm4-capacity-timeline-phase-b-end]] — ~/rdco-vault/06-reference/research/2026-05-18-hbm3e-hbm4-capacity-timeline-phase-b-end.md
[[2026-06-23-stratechery-memory-chips-china-microsoft-deepseek]] — ~/rdco-vault/06-reference/2026-06-23-stratechery-memory-chips-china-microsoft-deepseek.md

Web

dram hbm phase2 phase3 early signals