06-reference/research

cxmt dram capacity memory oligopoly risk

2026-07-03·research-brief·source: deep-research
memory-cyclecxmtdramhbmchina-techinvesting-thesis

CXMT's DRAM ramp and HBM timeline — is China's entry the exogenous shock that breaks oligopoly pricing discipline?

The question

What is CXMT's current DRAM production capacity, yield rate, and timeline to HBM production — and how likely is their market entry to break the three-player DRAM oligopoly's pricing discipline, threatening the memory capital-cycle thesis? Context: memory-cycle-v1(.1) is a long-only bet premised on Samsung/SK Hynix/Micron holding capacity discipline; the 2026-06-23 Stratechery piece flagged CXMT as a Phase-2 disruptor, and the vault has no dedicated coverage of Chinese-entrant progress — the single biggest un-researched risk to the thesis.

What we already know (from the vault)

What the web says

Convergences and contradictions

Synthesis for RDCO

Net threat to oligopoly pricing discipline over the next 4-8 quarters: MEDIUM — but decomposed, it's LOW on the thesis-critical HBM lever and MEDIUM (rising toward HIGH in the 2028+ window) on the commodity-DDR flank. The thesis is intact for the current Phase 2 window; CXMT reads as a Phase-3 accelerant, not a Phase-2 breaker.

On HBM — where the oligopoly actually extracts its 80%+ margins — CXMT is not a factor in the thesis window. Two generations behind, ~25% HBM3 yield, mass production slipped past 2026, and a hard base-die ceiling (no EUV, no TSMC, SMIC at 7nm) that no amount of state subsidy fixes on a 4-8 quarter clock. This is thesis-confirming: the vault's own disqualifier ("CXMT volume HBM3E, high-prob 2027") is outrun by reality. HBM premium pricing, and the crowd-out that starves commodity DRAM, stays structurally protected through at least 2027.

On commodity DDR4/DDR5, the picture is genuinely more uncertain and is the correct place to worry. CXMT is adding ~85k wspm/year, targeting DDR5 yield parity by late 2026, and openly intends to use price to take the low-to-mid end. What caps the near-term threat: (1) a >30% cost-per-bit disadvantage means CXMT can't sustainably undercut in a tight market without bleeding — today it prices near parity because the market is short; (2) TrendForce confirms contract prices are stable and the only observed weakness was a niche secondary-module channel; (3) the market is modeled undersupplied through 2028. The threat activates on a state-change, not a level: if/when the market flips from undersupply to balance, CXMT's low-margin volume becomes the marginal price-setter that deepens and accelerates the Phase 3 downturn — precisely the "China is the wildcard that forces Phase 3 from outside the big three" scenario the indicator brief named. It sets a lower ceiling on low-end/Asia-channel commodity ASP and shortens the runway on the far side of the peak; it does not break discipline while supply is still short.

Actionable read for the position: keep memory-cycle-v1.1 posture unchanged — this does not trip a disqualifier and the Phase 2 anchors still hold. But CXMT graduates from "narrative wildcard" to a tracked exogenous variable: instrument CXMT bit-share (the SemiAnalysis 9%→11%→12% path), DDR5 yield-parity confirmation (~late 2026), and any big-three contract-price crack that is not confined to the secondary channel. The moment two of those move together with the vault's inventory-days / ASP-rollover indicators, CXMT flips from accelerant to co-trigger and the Phase 3 timing pulls forward — most plausibly into the 2027-2028 window, not the next 4-8 quarters.

Open follow-ups

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Sources

Vault

Web