Concrete leading indicators of the memory capital cycle's Phase 2→Phase 3 turn
The question
What are the concrete leading indicators that mark the chip/memory capital cycle's Phase 2→Phase 3 transition (HBM/DRAM spot pricing, fab utilization, capex guidance, lead times)? Context: the RDCO investing thesis places us in Phase 2; the Markov strategy-pipeline needs observable, trackable phase-transition signals to be actionable rather than narrative.
What we already know (from the vault)
- The Markov pipeline spec is explicit that the capital-cycle phase ladder runs P1 tight-supply/rising-ASP → P2 capacity-announcements (←here) → P3 capacity-online/glut → P4 capex-cuts/rationalization, and that Layer 1's job is to track "observable leading indicators (capex announcements, fab groundbreaks, fab-utilization, lead times, book-to-bill, inventory days, ASP trend) + informed transition priors" — explicitly because there are too few cycles (~4-6 in 40 yrs) to fit a transition matrix [[2026-05-27-markov-equities-pipeline-spec]].
- The executable thesis already encodes mechanical exit/anchor triggers that ARE the Phase 3 markers: hyperscaler combined capex revised DOWN >10% across 2+ consecutive quarters; oversupply explicitly announced by 2+ vendors; DRAM contract prices declining 4+ consecutive months; HBM capacity-online matching/exceeding demand; a major maker announcing expansion that closes the bottleneck in <18 months [[2026-05-18-memory-cycle-v1-1]].
- The phase-history methodology log gives the historically-applied mechanical rule for a down-cycle entry: "DRAM spot declining 6+ consecutive months OR vendor margin compression >30%," plus capacity-announcement = "vendor publicly commits >20% capacity increase." It also flags the live regime-change risk: this AI-driven cycle may stay in Phase 2 plateau structurally longer than prior cycles (Castellano "HBM has broken the cycle" / Samsung capacity-discipline) [[2026-05-18-memory-cycle-v1-1-phase-history-notes]].
- The prior capacity-timeline brief already named the best-evidence Phase-B-end window as Q3 2026 - Q2 2027 and flagged Samsung's +47% wafer ramp (170k→250k/mo by end-2026) as borderline-triggering the "<18-month bottleneck close" disqualifier; the cleanest single milestone = "Samsung's 250k wafer/month target hit early" [[2026-05-18-hbm3e-hbm4-capacity-timeline-phase-b-end]].
- June Stratechery (Ben Thompson) corroborates we are still mid-Phase-2: HBM premium absorbs all disciplined capacity, commodity DRAM/NAND shortage cascades, and the oligopoly's restraint is the leading indicator of over-extraction; Chinese entrants (CXMT +700% YoY Q1 2026 revenue; YMTC 2x NAND by end-2027) are the new Phase 2 disruptor variable [[2026-06-23-stratechery-memory-chips-china-microsoft-deepseek]].
What the web says
- Pricing is still accelerating UP, not rolling over (Phase-2-confirming). 1Q26 DRAM industry revenue +81% QoQ; 2Q26 conventional DRAM contract prices projected +58-63% QoQ; HBM contract prices expected to "surge multiples higher in 2027" as 2027 HBM4 long-term agreements get negotiated (TrendForce, Jun 2026; TrendForce, Jun 2026).
- Pricing inversions are the late-tightness tell: DDR4 spot hit ~$2.10/Gb, exceeding HBM3E at ~$1.70/Gb, and server DDR5 ASP surpassed HBM profitability — a "historic first." These dislocations signal supply is maximally strained, i.e. peak tightness, not yet relief (TrendForce 2Q26 forecast).
- Capex is rising but deliberately NOT adding bit supply. 2026 DRAM capex ~$61.3B (+14% YoY) but TrendForce states it will have "minimal impact on bit supply growth in 2026" because spend goes to node migration (1-gamma/1c) and TSV/HBM packaging, not greenfield wafer capacity. Per-vendor: Micron $13.5B (+23%), SK Hynix $20.5B (+17%), Samsung $20B (+11%) (TrendForce, Nov 2025).
- The one aggressive capacity signal is Samsung's HBM ramp: ~250k wafers/month by end-2026 (+47% vs 170k), the largest single-maker addition this cycle and the textbook "defensive land-grab marks the end of oligopoly discipline" pattern (TrendForce, Dec 2025). SK Hynix is choosing DDR5 profits over a faster HBM4 ramp (TechTimes, Jun 2026).
- Lead times and allocation are at crisis-tightness (Phase-2-confirming): DRAM lead times >40 weeks; allocation-only frameworks prioritizing hyperscalers; spot buy activity +70.56% QoQ and DDR DRAM spot purchases "44x normal"; data centers projected to take ~70% of high-end memory in 2026 (VersaLogic; Supplyframe).
- Supply relief is dated to H2 2027-2028, not 2026. New fabs (SK Hynix M15X, Micron Idaho ID1, Samsung P4L/P5) "will not add meaningful DRAM capacity until mid-2027 to 2028"; a fab needs 3-5 years to contribute; SK Hynix chairman says the shortage could last "another four to five years." Oversupply is a "realistic possibility in 2028-2029 if AI demand moderates as capacity expands" (SHI; Supplyframe).
- The historical peak-signal sequence (uncoveralpha, the canonical cycle-mechanics piece the vault already cites): stock price leads fundamentals by 1-2 quarters → supplier inventory falls to 3-4 weeks at the tightness peak (vs 8-week normal; was 3.3 weeks end-Q3 2025, matching 2018 supercycle lows) → a wave of capex/fab announcements (50+ in 1995-96; capex >30% of production) signals consensus on peak demand → ASP peaks → gross margins peak then compress 2-3 quarters into the downturn (2018: 58.9% → 27%) → fab utilization sustained 95%+ right up until new capacity arrives (uncoveralpha).
Convergences and contradictions
- Strong convergence: Every primary indicator currently reads "still deep in Phase 2." Prices accelerating up, lead times >40 weeks, allocation-only, inventories at supercycle lows, and meaningful new wafer capacity dated to H2 2027+. The vault's "Q3 2026-Q2 2027 Phase-B-end window" and the web's "relief mid-2027 to 2028" agree the turn is not imminent in 2026.
- The single tension to watch: capex is rising (+14% DRAM) yet bit-supply growth stays minimal — this is the disciplined-oligopoly variable. The classic Phase 2→3 trigger is capex translating into wafer capacity; right now it isn't (it's going to node migration + HBM packaging). The turn fires when capex starts buying greenfield wafers AND/OR Samsung's 250k HBM wafer target lands on/ahead of schedule. Watch the composition of capex, not just the dollar level.
- Contradiction / regime-change risk: the "HBM has broken the cycle" hypothesis says disciplined capacity could hold the market in Phase 2 plateau far longer than the 4-phase model assumes (no clean crash). Counter-signal: Chinese entrants (CXMT/YMTC) are a non-oligopoly supply source the discipline can't control — they are the most likely agent to force Phase 3 from outside the big three.
Synthesis for RDCO
The Phase 2→Phase 3 transition is the cycle top, and it is detectable as a sequence, not a single print. Order the Markov Layer-1 feature set to fire on confirmation, weighting the earliest-turning signals highest. Define each as a binary observable with an explicit threshold so two raters agree (the phase-history discipline):
Supplier inventory days (earliest, highest-weight leading indicator). Currently ~3.3 weeks (matching 2018 lows = peak tightness). The Phase-3 precursor is inventory rising back toward the 8-week normal. Threshold: supplier DRAM inventory rises above ~5-6 weeks for 2+ consecutive quarters. This turns 1-2 quarters before ASP and is the cleanest non-price early warning. Source: vendor earnings + TrendForce inventory commentary.
Capex composition shift, not just level (the disciplined-cycle-specific signal). A dollar-level capex rise is necessary but not sufficient this cycle because spend is going to node migration. Threshold: 2+ vendors announce greenfield wafer-capacity expansion (vs node/packaging), OR Samsung hits its ~250k HBM wafer/month target on or ahead of schedule. Samsung's target hit early = supply landed faster than demand absorbed it = textbook top. Source: TrendForce capacity reports + vendor capex calls + the existing
/investing:edgar-watchhyperscaler-capex anchor (mirror it with vendor-side capex).ASP / contract-price rollover (the confirmation print). Threshold (from thesis + phase-history): DRAM contract/spot declining for 4-6 consecutive months, OR any one maker reports HBM ASP -10% QoQ. This is the lagging-but-unambiguous confirm; pairing it with #1/#2 above is what distinguishes a true turn from a one-month wobble. Source: TrendForce monthly DRAM/HBM bulletins (the DRAM-spot anchor CSV already feeds this).
Lead times / allocation normalization. Threshold: DRAM lead times compress below ~26 weeks AND allocation-only frameworks relax (suppliers quoting open-market again). Currently >40 weeks and allocation-only, so this has the most distance to travel — it is a confirming not leading signal, but cheap to track and hard to fake.
Fab utilization. Counterintuitively, sustained 95%+ utilization is a tightness signal; the Phase-3 tell is utilization softening from 95%+ as new capacity outpaces demand. Threshold: aggregate memory fab utilization declines below ~90% with new-capacity online. Lower priority (data is laggy and proxy-heavy) but include as a confirming feature.
Gross margin peak (lagging confirm) + stock price (noisy lead). Margin peaks (Micron ~80% currently) then compresses 2-3 quarters into the downturn — use as a confirmation that #1-#3 were right, not as a trigger. Equity price leads fundamentals 1-2 quarters but is too noisy to be a standalone Layer-1 state input.
Pipeline encoding. Layer 1 should not flip P2→P3 on any single feature. Recommended composite rule consistent with the thesis's "any TWO HIGH-severity anchors confirmed across 1-2 quarters": declare Phase 3 when (inventory rising >2Q) AND (ASP rolling over 4-6 months) — OR — when (Samsung 250k target hit) AND (ASP -10% QoQ at any maker). Everything else (lead times, utilization, margin, China entrant volume) raises the transition prior but does not alone flip the state. Critically, because the disciplined-oligopoly + China-entrant dynamics are genuinely new, the live cycle should be treated as "may-not-complete on the historical clock" — the pipeline should carry an explicit Phase-2-plateau state so it doesn't manufacture a crash date the supply curve doesn't support. As of June 2026 every indicator reads still-Phase-2; the earliest plausible turn-window remains Q3 2026-H1 2027, gated primarily on the Samsung wafer-ramp landing and inventory days lifting off the floor.
Open follow-ups
- Build the supplier-inventory-days time series (Micron/SK Hynix/Samsung quarterly DIO from earnings) as a new anchor — it's the highest-value leading indicator and the vault doesn't yet track it as a structured series.
- Add vendor-side capex composition tracking (greenfield-wafer vs node-migration vs HBM-packaging split) to the hyperscaler-capex EDGAR anchor — dollar level alone misses the disciplined-cycle wrinkle.
- Quantify the CXMT/YMTC volume trajectory and the bit-share threshold at which Chinese supply becomes the exogenous Phase-3 trigger the oligopoly can't discipline.
- Re-key the 2018 cycle "Samsung capacity-announcement → ASP rollover lag" interval to calibrate the exact lead-time of indicator #2 ahead of #3 (best single historical calibration point for the current window).
- Test the "HBM has broken the cycle" plateau hypothesis as an explicit backtest variant (current cycle does not crash; exit only on China-entrant disconfirmation or smart-money exit).
Related
- [[2026-05-27-markov-equities-pipeline-spec]] — the Layer-1 phase-tracker this feature set feeds
- [[2026-05-18-memory-cycle-v1-1]] — executable thesis; its anchor triggers ARE the Phase 3 markers
- [[2026-05-18-memory-cycle-v1-1-phase-history-notes]] — mechanical phase-transition rule definitions + regime-change caveat
- [[2026-05-18-hbm3e-hbm4-capacity-timeline-phase-b-end]] — capacity-online milestone timeline (Q3 2026-Q2 2027 window)
- [[2026-06-23-stratechery-memory-chips-china-microsoft-deepseek]] — current Phase 2 corroboration + China-entrant variable
Sources
Vault
- [[2026-05-27-markov-equities-pipeline-spec]] —
~/rdco-vault/01-projects/investing/2026-05-27-markov-equities-pipeline-spec.md - [[2026-05-18-memory-cycle-v1-1]] —
~/rdco-vault/01-projects/investing/theses/2026-05-18-memory-cycle-v1-1.md - [[2026-05-18-memory-cycle-v1-1-phase-history-notes]] —
~/rdco-vault/01-projects/investing/anchors/memory-cycle-v1-1/phase-history-notes.md - [[2026-05-18-hbm3e-hbm4-capacity-timeline-phase-b-end]] —
~/rdco-vault/06-reference/research/2026-05-18-hbm3e-hbm4-capacity-timeline-phase-b-end.md - [[2026-06-23-stratechery-memory-chips-china-microsoft-deepseek]] —
~/rdco-vault/06-reference/2026-06-23-stratechery-memory-chips-china-microsoft-deepseek.md
Web
- Rapid Contract Price Surge Drives 1Q26 DRAM Up 81% QoQ — TrendForce
- Tight DRAM Supply Gives Suppliers Greater Pricing Power in HBM, Contract Prices to Surge Multiples Higher in 2027 — TrendForce
- 2Q26 Memory Price Forecast — TrendForce
- Memory Industry to Maintain Cautious CapEx in 2026, Limited Impact on Bit Supply Growth — TrendForce
- Samsung Plans 50% HBM Capacity Surge in 2026 — TrendForce
- SK Hynix Choosing DDR5 Profits Over HBM4 Ramp — TechTimes
- Every Memory Cycle Ends the Same. Until It Doesn't. — uncoveralpha
- Supply Chain Brief: Memory Market Conditions in 2026 — VersaLogic
- Industry Experts Warn Current DRAM Shortage Could Last Until 2030 — Supplyframe
- The Impact of the 2026 Memory Shortage on Data Center Buyers — SHI